1. Field of the Invention
The instant disclosure relates to a ternary content-addressable memory; in particular, to a non-volatile ternary content-addressable memory (TCAM) 4T2R cell with RC-delay search.
2. Description of Related Art
Content-addressable memory (CAM) is a type of computer memory used in high speed searching applications. Content-addressable memory fast compares a string of input data with stored data, and outputs the address of matched data. Binary content-addressable memory is the simplest CAM for storing data with two states including “0” and “1”. Ternary content-addressable memory (TCAM) is for storing data for one or more bits in the stored dataword with three states. The first state is “0”, the second state is “1” and the third matching state is “X” (or “Don't Care”) which means always match.
The conventional ternary content-addressable memory comprises an array (all storage cells; 1 row as 1 entry, 1 column as 1 bit), a decoder for choosing which row to write, a main controller for producing control signals, a data-in circuit for writing data or searching data, a sense amplifier (SA) for sensing compared result and amplifying the result, and an output encoder for transferring the result into address which has matching data. In a write phase, writing data to the storage cell(s). In a search phase, comparing input data with memory content (all data in storage cells), and outputting the address of identical (matching) content.
Referring to FIG. 1B and FIG. 1C showing circuit diagrams of the conventional 16T SRAM-based TCAM and 12T SRAM-based TCAM. In FIG. 1A, six transistors constitute a storage part 11 connected to a bit-line BL1 and a word-line WL, six transistors constitute a storage part 12 connected to a bit-line BL2 and the word-line WL, and the compare logic 13 is a NAND logic (or a NOR logic) connected to search-lines SL1, SL2 and a match-line ML. In FIG. 1B, four transistors constitute a storage part 21 connected to a bit-line BL0 and a word-line WL, four transistors constitute a storage part 22 connected to a bit-line BL1 and the word-line WL, and the compare logic 23 is a NAND logic (or a NOR logic) connected to search-lines SL0, SL1 and a match-line ML. For the TCAM shown in FIG. 1A (or FIG. 1B), writing data is similar to the conventional SRAM, in which the state “0” is stored as to (1, 0) (for (SRAM1, SRAM2)), the state “1” is stored as to (0, 1), and the state “X” is stored as to (0, 0). For data search, the compare logic 13 (or 23) connecting the search-data pair and the storage-data pair will discharge the match-line ML if the search-pair is different from the storage-data pair.
However, for non-volatile memory (NVM), read disturb during reading which flips data in the storage cell should be reduced. Read disturb probably happens when large voltage stress is applied to the non-volatile memory or large current passes through the non-volatile memory. Meanwhile, more transistors in each cell occupy more circuit (or chip) area.